1. Field of the Invention
The present invention relates generally to the field of semiconductor device fabrication and more particularly to wafer cleaning.
2. Description of the Prior Art
Semiconductor devices, including the Back-End of Line (BEoL) interconnect structures thereof, include conductive lines and other features that are formed from copper. During semiconductor device fabrication on a wafer, the copper is typically deposited within trenches or vias defined in a dielectric layer. The copper and dielectric layers are then planarized to provide a smooth and planar surface on which to deposit additional layers. A common method for planarizing is chemical mechanical planarization (CMP). CMP processes typically leave a residue on the exposed surface of the wafer that must be removed prior to the formation of subsequent layers.
Typical approaches to removing the CMP residue involve washing the wafer. For example, the wafer can be washed first in an acidic solution and then in a basic solution, or first in a basic solution followed by an acidic solution. However, these methods are disadvantageous as they tend to remove copper, leaving the copper features recessed with respect to the surrounding dielectric layer. Other methods for removing the CMP residue expose the wafer to an energetic plasma to etch away the residue.
What is provided by the present invention are novel methods for removing CMP residue that do not harm either the exposed copper or the dielectric layer.